Description

The device is CMOS Dynamic RAM organized as 4,194,304 words x 4 bits. It is fabricated with an advanced submicron CMOS technology and designed to operate from a single 5V only or 3.3V only power supply. Low voltage operation is more suitable to be used on battery backup, portable electronic application. A new refresh feature called " self-refresh " is supported and very slow CBR cycles are being performed. It is packaged in JEDEC standard 26/24 - pin plastic SOJ or TSOP (II).

Features

• Single 5V ( %) or 3.3V ( %) only power supply

• High speed t RAC access time : 50/60 ns

• Low power dissipation

- Active mode :

5V version 605/550 mW (Max.)
3.3V version 396/360 mW (Max.)

- Standby mode :

5V version 1.375 mW (Max.)
3.3V version 0.54 mW (Max.)

• Fast Page Mode access

• I/O level :

TTL compatible (Vcc = 5V)
VTTL compatible (Vcc = 3.3V)

• 2048 refresh cycles in 32 ms (Std) or 128ms (S - version)

• 4 refresh mode :

- RAS only refresh
- CAS-before-RAS refresh
- Hidden refresh
- Self - refresh (S - version)