Description
The device is CMOS Synchronous Dynamic RAM
organized as 524,288 words x 32 bits x 4 banks. it is fabricated with an advanced
submicron CMOS technology and designed to operate from a singly 3.3V only power supply. It
is packaged in 86-pin TSOPII package.
Features
Single 3.3V ( ) power supply
High speed clock cycle time :
5/6/7/8ns
Fully synchronous with all signals
referenced to a positive clock edge
Programmable CAS Iatency (2 & 3)
Programmable burst length (1, 2, 4,
8 & Full page)
Programmable wrap sequence
(Sequential/Interleave)
Automatic precharge and controlled
precharge
Auto refresh and self refresh modes
Quad Internal banks controlled by
BA0 & BA1 (Bank Select)
Each Bank can operate simultaneously
and independently
VTTL compatible I/O interface
Random column access in every cycle
X32 organization
Input/Output controlled by DQM
4,096 refresh cycles/64ms
Burst termination by burst stop and
precharge command
Burst read/single write option
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