Description

The device is CMOS Synchronous Dynamic RAM organized as 2,097,152 words x 8 bits x 4 banks and 1,048,576 words x 16 bits x 4 banks, repectively. It is fabricated with an advanced submicron CMOS technology and designed to operate from a singly 3.3V only power supply. It is packaged in JEDEC standard pinout and standard plastic TSOP package.

Features

• Single 3.3V ( ) power supply

• High speed clock cycle time : 7.5/8ns

• Fully synchronous with all signals referenced to a positive clock edge

• Programmable CAS Iatency (2, 3)

• Programmable burst length (1, 2, 4, 8 & Full page)

• Programmable wrap sequence (Sequential/Interleave)

• Automatic precharge and controlled precharge

• Auto refresh and self refresh modes

• Quad Internal banks controlled by A12 & A13 (Bank select)

• Each Bank can operate simultaneously and independently

• VTTL compatible I/O interface

• Random column access in every cycle

• X8 and X16 organization

• Input/Output controlled by DQM

• 4,096 refresh cycles/64ms

• Burst termination by burst stop and precharge command

• Burst read/single write option